Controil for magnetic memory matrix



Nov. 17, 1964 R. w. HOEDEMAKER ETAL 3,157,854

CONTROLJ ROR MAGNETIC MEMORY MATRIX 5 Sheets-Sheet 1 Filed Jan. 9, 1961 Nov. 17, 1964 R. w. Hol-:DEMAKER ETAL 3,157,864

CONTROL FOR MAGNETIC MEMORY MATRIX Filed Jan. 9, 1961 5 Sheets-Sheet 2 NOV. 17, 1964 R. w. HOEDEMAKER ETAL 3,157,864

CONTROL FOR MAGNETICMEMORY MATRIX Filed Jan. 9. 1961 5 Sheets-Sheet I5 77M ING A,

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CONTROL TOR MAGNETIC MEMORY MATRIX 5 Sheets-Sheet 4 Filed Jan. 9, 1961 R. w. HOEDEMAKER ETAL. 3,157,864

CONTROL FOR MAGNETIC MEMORY MATRIX Nov. 17, 1964 5 Sheets-Sheet 5 Filed Jan. 9, 1961 mWSN tt INVENTORS United States Patent O This application is a continuation-impart application of application Serial No. 819,588, tiled June ll, 1959, now abandoned.

The present invention relates in general to the storage of information in magnetic core matrices or similar storage devices. Particular specific aspects of the invention relate to the use of magnetic core matrix as a storage medium for binary coded information representing the values of a number of variables and particularly to control circuitry which converts analog variable value indieating signals into binary coded form in the magnetic core matrix. Certain broad aspects of the invention, however, are not so limited.

Among `the general objects of the invention are to provide improved control means for setting (and resetting) the cores of a magnetic core matrix or other magnetic core device. A related object of the invention is to provide an improved means for selectively setting the cores of a magnetic core matrix or similar storage device under control of asynchronously or randomly related signals which, in the preferred application of the invention, include variable responsive signals. Another object of the invention is to provide control means as just described which are simple yet highly reliable.

All aspects of the invention will be disclosed in connection with a variable measuring and storage system wherein the value of each variable is indicated by the timing of a pulse generated by a pulse time modulator means. This means comprises a common reference signal source which generates a progressively varying signal which is compared with the analog signal or characteristic of each variable. When correspondence (or a given state of comparison) exists between the reference signal source and the analog signal or characteristic of a variable, a pulse is generated. Each time modulated pulse could be converted to a binary coded signal by gating the input of a pulse counter with the time modulated pulse. The pulse counter begins its count when the reference signal starts from zero or other minimum signal level. With this arrangement, individual pulse coun-ters and gate circuits are required. This is unsatisfactory from a number of viewpoints, one of which being the large number of counters that are required. lt is, accordingly, one of the objects of the present invention to provide a system for converting analog signals to binary coded signals where a large number of variables are involved and which utilizes a minimum of counting components.

ln accordance with one specilic aspect of the present invention, instead of providing individual counters for storing binary coded information on the values of the variables, a magnetic core matr`x is used as a storage medium in a manner Where the matrix performs the dual function of gating and storage. The core units of a matrix are usually arranged in adjacent rows and columns, the core units of each column having series connected signal input control windings extending to a common column input line or terminal, the core units of each row having series connected signal input control windings extending to a common row input line or terminal. Each core unit has a core made of a rectangular hysteresis material which is driven from a rst or reset state of saturation to a second or set state of saturation when halt current set pulses are simultaneously fed to Mice the common input terminals associated with the core. When half current pulses are fed to only one of the control win ings of a core, insufficient magnetomotive force is developed to drive the core from one state of saturation to another. A single pulse counter (or coding means as it is sometimes referred to) is utilized for the entire system and equally spaced timing pulses are fed to the counter, which may be a scale-of-two cascaded lip-lop counter. Each stage of such a counter is a flipflop circuit with a code output line extending therefrom which has one of two possible signal conditions indicating the binary state of the counter stage involved. The signal condition or" each counter output controls the presence or a sence of a halt current set pulse (sometimes referred to as a read-in pulse) at one of the common row input terminals of the matrix.

The time modulated pulse associated with each variable controls the timing for the feeding of a half current set puise `to the common column input terminals of the matrix, so that the output condition of the associated pulse counter stage is transfer ed or gated into the associated core unit of 4the column of the matrix at the approximate moment the reference signal and variable signal correspond. in the example of the invention being described, the time modulated pulses and the timing pulses which step the pulse counter are randomly related so that s rious count ambiguities could occur if a time modulated pulse occurs at the very instant the counter is being advanced to the next count. ln the scale-oftwo counter, a number of the digits frequently change in quick succession when a count is advanced by one unit. if the output of the counter is gated into the core matrix at an instant when only part of the digits undergoing a change have been modified, the error in the count stored in the matrix can be substantial (ie. much more than a one unit error). ln accordance with an aspect of the present invention, pulse delay and gating techniques are utilized to ensure the gating of the counter output into the matrix at a time when the pulse counter has been completely set to the current count. rlhe broader phase of this aspect of the invention is not limited to an analog to binary conversion application but extends to the general problem of gating information into a matrix where the control signals which eectuate the generation of the row and column half current set pulses have no definite time relationship.

ln accordance with still another aspect of the invention, a pulse forming means is provided for each variable which means responds to the associated time modulated pulse by generating a pulse of indeiinite duration. The termination of the latter pulse occurs when the function to be performed thereby has been completed. rhe outputs of each pulse forming means and pulse counter stage are red to separate and gate or coincidence circuits, sometimes referred to as column and row and gates. A given binary output state of a counter stage opens the associated row gate whereas the opposite binary state closes the associated row gate. Similarly, the presence of an output pulse at a pulse forming means will open the associated column gate and the absence ot such a pulse will close the associated column gate. Each of the and gates has a signal input extending to a source of read-in pulses, sometimes referred to as time gate pulses, which occur in synchronized but delayed relation with respect to the timing pulses which drive the common pulse counter. These pulses are most preferably derived by feeding the timing pulses to a frequency doubler and delay means which provide pulses at twice (or a multiple) of the basic time pulse repetition rate and spaced from the timing pulses. These pulses, either directly or through associated pulse expander means, feed the signal input terminals of the various aforesaid column and row and gates. When the time gate pulses occur when the associated and gates are open, half current set pulses are generated which are passed through the control windings of the associated matrix core units. The trailing edge of the time gate pulse passing through an open column and gate is operable to terminate the output of the associated pulse forming means tot avoid or minimize the possibility of the generation of additional unwanted half current set pulse which could gate erroneous information into the matrix.-

In accordance with 'anotherr aspect of the present invention, instead of feeding the output of each column and gate directly to the matrix, this output (or the output of another set pulse supplying means) is fed to a read-in control Winding of a drive core unit having a core with a rectangular hysteresis characteristic.y The latter pulse drives the core from a reset state of saturation to a set state of saturation to induce into a first output Winding thereof a half current matrix set pulse. It takes a nitetime to drive a drive unit core between extreme states of saturation, so that the pulse fed to the read-in control winding must be of suncient duration to enable the complete driving of the core between extreme states of saturation. Otherwise, the pulse induced into the first output winding of the drive core unitiwill be insufficient properly to set the matrix core units, with the result that erroneous or ambiguous data will be stored in the matrix.

In the case of the randomly generated time modulated pulse referred to above, it is quite possible that there will be only partial coincidence between the pulse inputs to the column and gates (i.e. the time modulated pulse will be initiated during a time gate pulse so that the output of a given and gate is a pulse of-insuiiicient duration to effect the complete driving of the drive unit core to its set state of saturation).

In accordance with another aspect of the invention, a feedback winding is provided on the drive unit core which is coupled to the preceding circuits in ay manner which will extend the duration of the set pulse fed tothe read-in control winding thereof until the core has been completely driven between its extreme states of saturation.

The above and other objects, advantages and features of the invention will become apparent upon making reference to the specification to follow, the claims and the drawings wherein: f

FIGS. 1 and 1A together form a detailed box diagram of a preferred form of variable measuring and storage system constructed in accordance with the present invention;

FIG. 2 is a timing diagram of various pulses lwhich are present in the system of FIGS. 1 and 1A;

FIG. 3 is a circuit diagram of a core drive unit shown in box form in FIG. 1 and constituting an aspect of the present invention; y

FIG. 4 is a rectangular hysteresis curve for the coreV of the core drive unit shown in FIG. 3; Y

FIG. 5 is a circuit diagram of an exemplary frequency doubler and pulse delaymeans shown in box form in FIG. 4 for generating properly shaped and timed gate pulses, which means are shown in block form in FIG. 1; and f f FIG. 6 is a circuit diagram of an exemplary pulse forming means, gated ampliiier and core drive means shown in box form in FIG. l. n Y Y' Reference should now be made to the box diagram of FIGS. 1 and 1A which show a preferred form of the present invention. As previously indicated, although certain aspects lof the invention are not solirnitedr, the

. exemplaryform of the invention is disclosed in connectionl with a variable measuring and storage system ywherein the values of the variables are indicated by the timing of respective pulses generated by associated pulse time modu-V lator means. In FIGS. 1 andy lAfthe pulse time modulator means 'includes a common signal generator 2 `which provides a saw-tooth signall cutout waveform 2a, lThe waveform 2a vmaybe an electrical signal, particularly where the' variables involved are indicated by electrical analog signals or, for example, a pressure signal where the variables areA pressure variables. The signalsources indicating the values of the variables are generally indicated by reference numeral 4. These sources could be thermocouples in the case of temperature variables, bellows-operated potentiometers in the case of pressure variables, or even the primary variables in the case Where the signal generator 2 generates a signal corresponding to the variable as above indicated. The time modulator means further includes comparator means 6 vassociated with each variable which means has inputs 6 and 6". Each signal input 6 is coupled to the output of the common signal generator 2 and each signal input 6". is connected to the associated variable signal source 4. Each comparator means 6 produces an output signal, preferably a pulse, at the moment the values of the input signals fed to the signal inputs 6 and 6" are equal or reach a given state ofV comparison.

The comparator means 6 may take any one of a number of well known forms, as, for example, the core type comparator circuit disclosed in U.S. Patent No. 2,739,285, granted March 20, 1956. Alternatively, it'could include a capacitor transducer device as disclosed, for example,

ing a common plate of two capacitors is caused to move in accordance with the differences in pressure applied to the opposite sides thereof. In such case, the two variable capacitors are placed in corresponda(r arms of a Wheatstone bridge circuit which effectively produces a null at the instant the pressures are balanced.

The timing of the outputs of the various comparator means 6 with respect to the initiation'or beginning of the saw-toothed signal waveform 2a at the output of the common signal generator 2 are an indication of the values of the associated variables. Meansare provided for indicating time with respect to the beginning of the waveform 2a, which means most advantageously comprises a common pulse counter 8 (sometimes referred to as a coding means). The pulse counter has an input 8 which may be directly connected to the output of a gate circuit 1t) or indirectly thereto through an intermediate pulse shaping means suchy as a square wave generator 12 synchronized by the output of the gate circuit 1t). The gate circuit 10 has two inputs 10 and 10". The input 10 extends to a timing pulse source 14 which provides timing pulses at a given predetermined frequency. The timing pulses are coupled through the gate circuit 10 when the other input 10 receives a gate-opening signal from a control circuit shown as a flip-flop circuit 16. The flipiiop circuit 16 has an input 16 which is triggered into one of its conditions of operation by a set pulse fed from a suitable timer unit 18 at the4 instant the output signal Waveform 2a of the common signal generator 2 begins a new cycle. The iip-flop circuit 15 has'a second input 16 coupled toV the timer 18 which feeds a reset pulse thereto when the saw-toothV waveform 2a reaches its greatest magnitude. The startend reset pulses generated by the timer unit 1S may also be'used to synchronize the operation ofthe common signal generator 2. It is apparent that the techniques for synchronizing the operation *of the common signal generator 2 and the flip-flop circuit 16 are similar to those found in radar or invtelevision timing circuits and the like so that a description of ,a i

mentioned timing pulses and the resetting of the flip-flop l circuit closes the gate 10. It is apparent. that the pulse count accumulated Vin the pulse counter 8 at .any instant isa measurerof the yvalue of the output of the lsaw-tootl'i waveform 2.a. The pulse counter 8 rnost advantageously alavesa comprises a scale-of-two counter compri flop circuits Sa eacb of wb first and second s g al (O exist Witten the ass elated i set and reset. T'ne outpu o tbe various stages of the pulse counter collectively are sometimes referred to as binary bit ou its of the louise co;v te lie l signal condition of tlie nrst 'flip-flop circuit or tne counter represents 20(1), for the second flip-flop circuit 21(2), tor the t'nird flip-liep circuit 22(4) and for tlie ntli stage Zln-U. The number represented by tire coded outuuts considered collectively is tlie sum of Adie numbers represented by the l signal outputs o the 1pulse counter.

In a manner to be described, tbe pulse time modulated output of each cocinar tor means o gates tne binary bit outputs of tbe counter into tire associated column of core units or" a magnetic core matr'x storage unit generally indicated by reference numeral r3 The matrix 1% may be a conventional core matrix con rising adjacent rows and columns of i agnetic coro units 253, tb re being one column ot core un for each variable, and the corresponding core units in ne various columns of core units constituting a row of core units. column core unit, sometimes referred to as a binary bit storage unit, is associate with one of tbe outputs of tire pulse counter Each core unit may con e a ring of magnetic material preferably gular liysteresis curve, a first column control i, i lilla, a row control winding 2de, and an ou sut wi rougir single column Control winding ,slib could suffice, it is preferred that a second column control winding 2% be provided.

irg cascaded ilipn lies an output d at v' 'cn d l) output cond. iiop circuit is respectively ln a manner conventional ic core matrices7 the corresponding or lirst column control wind s Zbl-Z1 of each column of core unit e connected in se s, one

end of tire series circuit being connected to a common signal input ter 'ual or line sometimes referred to as a variable signal input terminal or line, since it receives a pulse timed in accordance with tine value of tlie associated variable. The other end or tbe series circuit may be connected to ground. Sir ilarly, where a second column control winding 295' is used, the column control windings oi each column o core units are connected in series, with one end oi tire series cir extend ing to the terminal or line Zfrtne other end connec to ground. The row control windings 2de of each row7 of core units likewise connected in series, with end of the circuit connected to a comrcon signal terminal or line 26, sometimes referred to as a read-1n signal input terminal or l and tire other end connected to ground. The output ./indings 25M oi each row of core units are connected series with one end connecting to a common row output ter 'il 26 tbe otr er e. connected to ground. As is co entional, tire various corresponding column row windings are eacli 'c rmed by passing a single wire tls-rough tire various rings of core material forming tbe row or column oi core units involved.

The various row output lines 2e extend to tbe inputs of various illu-liep cir ts 28 collectively forn g output register The t. sence oi cutout pulse at an output line 2o will set t'ne associated llipntlop one of its conditions and tlie Tif-sing tbc common reset line 3% will rese e lirp J:iop ci will appear, tne information stored in tlie various columns ot core units of the matrix are periodically fed to the output register' flip-tions in succc ion, with the register being reset before it receives the inzormation stored in the next column or" core units to be fed into tire output register.

ln reading information into tbe magnetic core matrix 18, simultan-:ous set or read-in pulses of a given polarity, commonly referred to as 1nali current ues, are fed to one of tlie con. un windings and row control winding 2de of a given storage unit is to be driven to a set state ot satur^tionlTlG. 4 shows a typical hysteresis characteristic of the rectangular bysteresis core material wherein tbe upper generally horizontal section X will be considered a set state of saturation and tlie corresponding generally horizontal lower section Y will Je considered a reset state of saturation. If the core is in the reset state of saturation Y, the magnetoniotive force of two one-halt current set pulses is required to drive the core from tbe Y to the X state of saturation. Similarly, a magnetomotive vlforce produced by the sum ot two or .lt current set pulses but applied in the opposite d ction is required to reset the core, that is, drive tlie same from an X to a Y state of saturation.

it is apparenL tliat the timing of the output pulse of a given comparator means 6 is a random timing, that is asynchronously relate"l to tlie timing pulses. As will rear, bait curro. pulses synchronously related to tbe -g pulses are red to the matrix row input lines 26 associated with a counter output having a l signal output condition, and so a problem exists in providing a time modulated purse corresponding to tl're value of the associated variable which is concurrent with the feeding ot readin pulses to tlie matrix row input lines 26. The random timing o tlie or out of a comparator means 6 also could create a count ambiguity if it occurred during the small interval of tine tne pulse counter 8 is responding to a timing pulse.

in accordance with one aspect of the invention, the output ot tbe square Wave generator l2 (as sliown in the timing di m, FG. 2b), which is synchronized with the timing pulses Flo. 2a, is fed to a frequency doubler and delay means 35, wnicll will be described in detail er. The frequency doubler and delay means provides a series of narrow pulses 37 (FlG. 2c) of a given polarity at twice the frequency oi the timing pulses and delayed with respect thereto. These pulses are operable to trigger a number ot pulse formi e iieans including a col si snot multivibrator and a single shot nuit. Abrator All associated with eacn matrix row input line 26. n single sliot multivibrator 39 provides two pulses per timing pulse (FIG. 2d) referred to as column time gate pulses, each sucli time gate pulse, for example, being ten micro-seconds long. Each row single sliot multiviorator il produces two time gate pulses la per timing pulse (FG. 2g), each such time gate y .lse, for example, being twenty micro-seconds long. lt siculd be noted that these pulses are delayed appreciably with respect to the occurrence of the timing pulses FIG. 2a so that tlte pulse counter is completely set to the new count before tlie time gate pulses are generated.

rElie row time gate pulses are fed to the respective inputs of row gate circuits 46. These gate circuits (as well as ga e circuits associated with the column signal input circo to 'ce described) are also sometimes referred to as coin nce means since tne opening of the gate or the generation of a given control output thereat re quires tlie presence of simultaneous signals of a given polarity or type at the two inputs thereof. The row gate circuits fs-5 have second inputs 46 coupled respectively to tne binary code bit outputs S of the pulse counter The l output state ot an output of tne pulse counter S effectively opens tlie associated gate circuit do or prepares tbe same for producing an output when a time gate pulse is concurrently fed to the gate circuit involved. Accordingly, twenty micro-second gate pulses will appear at tire output or" any gate circuit associated with a counter output having a l output state. The output of tbe gate circuits are respectively fed to suitable amplifiers whose outputs, in turn, will be half current set pulses ted to the associated matrix row input lines 26.

Referring now to the input circuit associated with eaciu column of tbe matrix l, the output or each comparator means is fed to a signal input circuit in -aiding a pulse forming l.eans most advantageously in the t'orm of a single snot multivibrator. This multivibrator is triggered into operation by the time modulated pulse at the e, teased output of the associated comparator means to provide a pulse such as lthat indicated in FIGS. 2e or 2h. As will appear, the pulse output of the multivibrator 50 preferably has an indefinite duration, the termination of each output pulse being dependent upon the completion of a gating operation to be described. It should be noted that the initiation of the output of the multivibrator 5i) shown in FIG. 2e occurs prior to the initiation of the column and row time gate pulses, whereas the initiation of the output of the multivibrator Sii shown in FIG. 2h occurs during the generation of a column time gate pulse. As will appear, the latter situation creates problems which are overcome by features of the invention to be described. The output of the multivibrator 5i), which is sometimes referred to as a variable responsive multivibrator to distinguish it from the aforementioned row and column signal shot multivibrators 39 and 41, is fed to one of the inputs 52 of a gate circuit 52 which is shown as a combination gate and amplifier stage. The presence of a multivibrator output pulse effectively opens the gate circuit 52 to enable passage therethrough of the input signal applied to a second input 52 of the gate circuit 52. The second input 52 is connected to the output of the column single shot multivibrator 39 which comprises the aforementioned ten microsecond time gate pulses 39a. Thus, when the gate circuit 52 is open, the associated time gate pulses pass through the gate circuit. At the instant of occurrence ofthe trailing edge of a time gate pulse fed through the gate circuit 52, a control signal is fed back to the variable responsive single shot multivibrator 5t? to terminate the generation of the output pulse thereof. It should be noted that the gate circuit 52 receives two time gate pulses per cycle both of which would pass through the gate circuit 52 if the output of the variable responsive single shot multivibrator Sti were not terminated prior to the second pulse. if the time modulated pulse output of the comparator means 6 occurred between thegeneration of the time gate pulses 39a within a given cycle of operation of the system, unless the output of the multivibrator 50 were terminated immediately after completion of the second time gate pulse, the gate 50 could remain open for a subsequent timing cycle thereby feeding incorrect information into the associated column of core units. The feedback control referred to, therefore, provides a high degree of reliability in the operation of the input circuits to the storage matrix 18.

In accordance with a broad aspect of the invention, each gate circuit 52 may act as an amplifier or the output thereof may be fed t0 a separate conventional amplifier to provide a half current set pulse which is fed to the signal input line 22 of the associated column of core units of the matrix 18. However, in accordance with an aspect of the present invention, a unique core drive means S45 is provided in each signal input circuit which has a general application Vin the control of the setting and resetting of a storage matrix 18, although it has particular utility in the variable measuring and storage system now being described. Reference should now be made vto FIG. 3 which shows the core drive means in detail. y Y

The core drive means isa transformer having a vcore 54a made of magnetic material having a rectangular hysteresis characteristic like that shown in FIG. 4. lThe core drive means 54 has two extreme states of saturation to be referred to as a set state of saturation indicated by the portionV X of the hysteresis curve and a reset state of saturation shown by the portion Y of the hysteresis curve. The core has a read-in control winding 5427, one end of which represents an input 54 to the core drive means shown invFIG. l leadingto the output of the gate circuit 52. The other end of as a common or ground line. application of the core drive To illustrate a generalized means 54, the input circuit sive to a first set the winding 54!) is shown t to the Winding 54!) is shown` in box form as a read-in pulse circuit of agencralized type. The output of the gate circuit 52 or Vthe generalized-read-in pulse circuit shown in FIG. 3 produces a set pulse of sutiicient ampliwinding on` the core.

O zo tude and duration normally to drive the core 54a from a reset to a set state of saturation. The transformer has a first output Winding 54e having a suiiicient number of urns that a half current set pulse for the matrix 1S Will be induced therein when the core is driven to its set state of saturation. A rectifier 56 is shown connected between one end of the output Winding 5de and the associated common matrix column input line 22. The other end of the winding 54C may be connected to ground. The rectifier S6 is connected to pass the half current set pulses referred to above and to block current flow when thecore 54a is reset. Since it takes a finite length of time to drive the core between its extreme states of saturation, it is apparent that the half current set pulse must have a suflicient duration to accomplish this result. l

As previously indicated, the pulse fed to the input S4 of the core drive means 54 is normally a pulse having the duration of a column time gate pulse 39a, which is a ten micro-second pulse in the exemplary form ofthe invention being described. If the duration of the set pulse fed to the transformer is appreciably less than ten micro-seconds, the pulse may be of insufficient duration to drive the core 5dr:V fully to its set state of saturation. As previously indicated, where the time modulated pulse output of the comparator means 6 is initiated during the generation of a time gate pulse 39a, only a fraction ofthe time gate pulse will pass through the gate circuit 52, as indicated in FiG. 2a which may be of in suicient duration to drive the core 54a fully to its set state saturation. The pulse output induced in the output winding 54a in such case would be a narrow pulse of an amplitude and duration which mayA be insuiiicient completeiy to set the associated cores of the storage matrix 1 8. This would create ambiguities or errors inthe information stored in the matrix.r The presence of relatively small unwanted pulses in the circuit leading to the read-in control winding 54h could drive a partially set or reset core 54a fully to saturation and thereby produce a pulse output in the output Winding 54e at a time when such such pulse should not be generated. When the core 54a is fully driven to a set state of saturation, any unwanted set pulses fed to the winding 54a will have no effect because the core 54a being fully set will not couple any change in magnetic flux to the output Winding 54C. The drive means 54, in such case, is only responpulse which enhances the reliability of the system. Y

To ensure that the initial set pulse fed to the read-in control winding 5415 has a 's uiiicient duration under all conditions, a feedback winding 54d is provided on the core 54a. One end of the feedback winding is connected byta conductor S7 to a part of the read-in pulse circuit which, in the embodiment of ltheinvention shown in FlG.l

Lis most advantageously the gate ycircuit 52; The other' end of the winding 54d may be connected to ground. While Vthe core 54a is being driven between its extreme saturation states, the Vflux' conditions in the core are changing so that a voltage is induced in the feedback 54d is utilized to sustain the Aduration of the set pulse fed tothe read-in controlv winding Sab in any suitable way, one of which will be described later on in the specification in connection with the cirthe feedback Winding cuit shown in FIG. 6.

As soon ascore 54a is fullydriven to a Yset state of saturation, ,thevinduced voltage in the'feedback Winding 54d comes .tofan end which in turnresults'in thev termination of the set pulse fed to the read-in control Winding 5415. The resultant pulse generated in the'first output winding 54C due to the action ofy theffeedback winding 54d is shownlin FIG. 2j. It is apparent from FIG. 2 that the halfr current pulse output lof the drive means 54 yunder the circumstancesvnow being described will be in the neighborhood of ten micro-seconds and that the beginning of this pulse occurs at some point during the The voltage which is induced in generation of the column time gate pulse shown in FIG. 2d as above explained. Since the setting of the cores or" the matrix lil requires coincidence tor at least ten micro-seconds between the half current pulses fed to the column and row control windings thereof, the time gate pulses fed to the matrix row input lines 2o must be greater than ten micro-seconds, in tact approximately twenty micro-seconds, to taire care of a situation where the time modulated pulse involved begins at a point near the end of a time gate pulse. rThis is the reason why the row time gate pulses have a twenty micro-second duration.

ln order to read out inormation stored in a column o core units of the storage matrix i3, it is necessary to reset any cores thereof which were previously set. This results in the generation of a pulse in the output winding ZtE-d of any such cores, which are ted to the associated flip-flop circuits of the output register so as to set the same. The cores of the matrix can be reset by feeding haii current reset pulses of opposite polarity to the aforementioned halr" current set pulses simultaneously through the row and column control windings of the matrix core involved. However, in accordance with the present invention, reset of any core of the matrix is obtained by feeding a full current pulse to the column control winding 21N), it this is the only column control winding, or through the aforementioned column control winding 20h. A second output winding 5de is provided on each transformer core 5ft-n so that a full current pulse is generated in the winding 'site when the core 54a is driven trom the set state of saturation to its reset state o saturation. A rectiier 59 is connected between one end of the winding 54e and the associated matrix column input line 24. The other end of the winding Sie may be grounded. The

rectifier 59 is connected to pass the full current pulse generated by the resetting ot the core and to block any pulses when the core is set. rElle core Sti-a is reset by means of a read-out control winding df wound on the core which winding is connected to a read-out pulse circuit. The read-out pulse circuit generates at the appropriate time a reset pulse of proper polarity and duration to drive the core 54a from its set to its reset state ot saturation. ln this manner, a full curernt pulse is generated in the output winding 54e.

ln the case where only a single matrix column control winding Talib is provided for the matrix core units, the output of the second output winding 5de of the drive means 5d is connected to the matrix column input winding 22 through the rectr r 59.

The readout pulse circuit in FlG. l may include a stepping switch ot any suitable type having a number of stationary contacts of and a wiper 64b which makes progressive contact win the contacts each time a stepping switch solenoid oli-c is pulsed. As is conventional in stepping switches, the solenoid 64e controls a normally closed switch odd which opens each time the solenoid 61E-c is energized to advance the wiper 64b one contact position. The switch is accordingly connected between one end of the solenoid 54e and a line ed leading to a common puise line 6"?. The pulse line 67 at the appropriate time receives read-out pulses from a timer 18', which pulses are also Jfed to reset lines 39 and 32 leading respectively to the reset terminals of the output register iii -iops E@ and the pulse counter flip-flops da. A read-out operation is carried out after the termination of a measuring cycle, that is after the generation of a sav -tooth waveform by the signal generator Buring this period, the timer i8 sends a plurality oi readout pulses to the solenoid elle so that all of the stationary contacts ot the stepping switching 6d are scanned. The stationary contacts of the stepping switch extend respectively to the readout control windings Edf of the .core drive means 5o associated with the various columns oi the matrix The stef ng switch wiper 6ft?) is connected to an input circuit including a pulse delay means 63 whose input is connected to the pulse line 67, and an lll) amplifier 7l) which provides an amplified pulse output ot suilicient amplitude and duration to constitute a reset pulse which, when fed to one of the read-out control windings Edf of the core drive means 54, will reset the associated core 54a. The purpose o the delay means ed is to delay the pulses which elect read-out of the information in the matrix until the stepping switch wiper 64b reaches the next contact oda. ln this manner, the information stored in the various columns ot the matrix are sequentially fed to the output register flip-ilops 2S which are reset as above explained before receiving signals from the succeeding columns of the matrix. rhe ilipllops 2.8 have outputs 2S which are fed to suitable storage or recording means (not shown).

Although the components shown in box form in FG. l are lino-wn Atypes of components, it would be helpful to disclose exemplary circuits .tor a few of them. These include the frequency doubler `and delay means 35, and the signal input circuit to each column oi the matrix including the gate circuit 52, the associated variable responsive single shot multivibrator 5d, the feedback circuits between the core drive means 5d, the gate circuit 52 and the multivibrator Eil.

Reference should now be made to 5 which shows an exemplary circuit for the frequency doubler and delay means 35. The circuit there shown is essentially a tliplop circuit 73 having a mag?. tlc core delay means *l5-'75 in the output circuits thereof and a summing circuit 77 connected to a cormon output circuit 79. rthe hip-lop circuit includes a pair of PN? type junction transistors Slt-8l having emitter electrodes Sila-tile' connected to a common ca. esistor biasing network in turn, connected to ground. The collector electrodes or Stb of each `transistor is connected through associated parallel capacitor-resistor feedback network :EL: or to or. The c and Sie are connected tlirousfh 7 3" and a common re tor to the i i 9d of a source @il ci positive direct current biasing potential. The collector electrode Sib of the transistor l is connected through a winding torming part of the delay means 75. winding 9i is wound upon a toroidal core @2 made of a rectangular hysteresis material. The core `has a biasing winding v und around the same core. One end of the biasing winding is connected through a variable resistor 9S to ground. The other end of the biasing winding is connected to the negative terminal 9d of a source of negativ@ energizing potential 96. The winding il is connected through resistor 97 to the negative terminal 95. The variable resistor provides la variable control over the degree of initial saturation or unsaturation or" the core and in so doing provides a control over the time it takes to drive the core to` an opposite state of saturation when transistor 8l becomes conductive.

The collector electrodes Sib of the transistor 3l is connected through a winding -l of the delay means 7S' which is identical to the core delay means 75. The windn" 9i is accordingly wound upon a toroidal core 92 the base elec^^ode die or lc of the other transrst base electrodes spective resistors D made oi a rectangular hysteresis material. The core has `a biasing winding 93 having one end connected through a variable biasing resistor to ground and another end connected through resistor 97 to the negative terminal 26. A conductor ld@ extends between tie iuncture oi resistor @"7 and the winding Sll to a series circuit of a capacitor itil and a resistor idf; connected to ground forming a differentiating network. Similarly, a conductor Mld extends between the juncture of resistor 97 and the winding Qi to `a series circuit of a capacitor mi' and a resistor 163 connected to ground and forming a differentiating network. A rectifier lilo' connected tot pass a negative pulse developed across the resistor 3 is conming circuit 77.

1 1 pass negative pulses developed across the resistor l11.33 is connected between the juncture of resistor 103 and the capacitor 161', and .the common point 167. A resistor 169 is connected between the common point tu? and the negative terminal 96 of the energizing voltage source 96. The common point 107 is also connected to the base electrode 111 of a PNP juncture type transistor whose emitter electrode is connected to ground and whose collector electrode is connected through -a resistor .HB9 tothe negative terminal 96.

The two transistor flip-Hop circuit 73 is essentia ly a free running multivibrator which produces a high current condition in the transistors 81 and 81 varying the cur-rent flow in the biasing windings 93 and 93', the precise -timing of the leading and trailing edges of the square wave output ofthe dip-Hop circuit lcan be varied. The diierentiating networks and the connections of the rectiers 195 and 19S of the summing circuit 77 -to 4the common point M7 produce at point 1527 a series of negative pulses occurring at twice the pulse repetition rate at which the square wave Hip-llopgenerator 73 operates. As previously indicated, these negative pulses are fed to the column single shot multivibrator 39, el, etc. which generate the row and column time gate pulses.

Refer now to FIG. 6 which shows a circuit diagram for i the signal input circuit associated with one of the columns of the storage matrix 1t?. This signal input circuit includes the aforementioned single shot (variable responsive) multivibrator 59 comprising a pair of PNP junction transistors 114-114. The emitter electrodes 114e and 114g of these transistors are connected toa common resistor 115 connected to ground. The collector electrodes 114-b and 114/J of these transistors are connected through respective load resistors 116 `and 116 to the negative terminal 95 of the (-15 volt) energizing voltage source 96. The base electrodes 114e and 114C of the transistors are connected through resistors 118 and 11S to ground. The collector electrode 114e of transistor 114 is connected to the base electrode 114C oftransistor 114 through a parallel circuit comprising a capacitor 1243 and a resistor 122. The collector electrode 114-b of transistor 114 is connected tothe base electrode 114C of transistor 114 through a series circuit ot a capacitor 124 and a resistor 126. With the circuit arrangement described, the transistor 114 will be in a normally conductive state and the trausistor 114 will be in a normally non-conductive state. The one shot multivibrator circuit 5t) is triggered into operation in any suitable way, as for example, by the feeding of a negative pulse from the output of the comparator means 6 through a capacitor 128 to the base electrode 114C or" the transistor 114. This triggers the transistor 114 into a conductive state which, in turn, renders the transistor 114' non-conductive for a maximum period determined lby the time constant of a circuit including the capacitor 12u. This period, for example, maybe several hundred micro-seconds.V However, this time constant is so long that the return of the multivibrator to its normal quiescent state of operation may be normally determined by the timing of a pulse fed through the capaci-tor 124 and resistor 126 to .the base electrode of 114e from the output of the gate circuit 52.

The gate circuit 52, as illustrated, includes a pentode 13u. A conductor 132 extends from the plate, circuit of the pentode 130 through a capacitor 134 and resistor 136 to the coupling capacitor 124. WhenV the Vpentode tube 13G-is rendered highly conductive (ile. when the gate is opened) at the beginning of a time gate pulse,k a resultant negative going pulse at the plate circuit is coupled to the capacitor 124. This negative pulse fed to the base electrode 114e of the transistor 114 will maintain conduction of the transistor 114 so that Vnothinghappens to the multivibrator at this time. However, when the pentode 13u becomes non-conductive .(i.e. theV gateA circuit is closed) at the trailing edge of the time gate pulse, a positive going pulse'is coupled through the capacitor alternately. By

l2 124 to the base electrode 114C to thereby render the transistor 114 non-conductive, which terminates the single cycle of operation of the one shot multivibrator 5i).

As previously indicated, the output of the one shot multivibrator 50 along with thevtime gate pulse controls the opening of the gate circuit S2 which is, in essence, an and gate or coincidence circuit. To this end, a conductor `137 is connected between the collector electrode 11411 and a resistor 138 connected to the suppressor grid e of the pentode 130. During the quiescent state of the one ,shot multivibrator 50, the potential at the collector electrode 114b is a negative potential which is coupled to the suppressor grid 13th: to thereby render the plate circuit of the pentode non-conductive. When the transistor 114 is rendered conductive, the potential of the collector electrode 114b and the suppressor grid 136a is near ground potential which enables the plate circuit of the pentode i to conduct provided the voltage conditions at the other control grid 13M of the pentode will permit it. The cathode 139C of the pentode 130 is connected to ground and the plate 13M thereof is connected through the aforesaid read-in control winding 54h of the transformer or core drive unit 54 previously described in connection with FIG. 3. The read-in control winding 54!) is connected through a resistor 140 to the positive terminal 142' of a source of (150 volts) direct current voltage 142. The screen grid 136e is connected by a line 143 to the juncture of resistor 14) and read-in control winding 54h. The control grid 13rlb of the pentode 130 is coupled to the aforesaid ten micro-second time gate pulse output of the column single shot multivibrator 39 shownV in FIG. 1. It is assumed that the output of the multivibrator 39 is a pulse which goes from minus 15 volts to 0 and back to minus 15 volts. This pulse is fed to the control grid 13% through an unique v circuit which includes the feedback 54d of the transformer 54 and a resistor 145. During the ten microysecond time gate pulse, the plate circuit of the pentode 139 will be conductive provided the variable responsive multivibrator 59 has a pulse output. As previously indicated, a voltage will be induced into the feedback winding 54d during the driving of the core 54a of the transformer 54 from a reset to a set state of saturation. The connection of the control grid 13% of the pentode 130 to the feedback winding 54d is such that this induced voltage will continue to render the pentode 139 conductive even after the termination of the timegate pulse until the core 54a has been completely saturated. Then, the pentode 130 will be rendered non-conductive again and, as previously indicated, the resultant positive voltage appearing at the plate 13611 will be in a direction to terminate the pulse output of the variable responsive multivibrator 50. f

The circuitry shown in FIG. 6V for the rst and second output windings 54C and 54e of the transformer is substantially as shown and described in FIG. 3, Vexcept for the inclusion of resistorsV 147 and 149 in these circuits. The read-out control winding 541 as shown in FIG. 6 has one end connected through a resistor 150 to the (300 Vvolt) positive terminal 151 of the direct current supply i source 142 and the other end connectedV to the stepping switch 64 in a manner previously indicated. It is apparent that the potentialy of the pulse fed to the readout-control. winding 54]c from the stepping switch is a ground or negative going pulse.

It should be vunderstood that numerous modifications may be made in the preferred form` 0f the invention described above without deviating from the broader aspects of the invention. ,f

What We claimA as new and desire to protect by Letters Patent of the United States: q

1. A control, circuit for setting and resetting vmatrix magnetic core storage units, saidy control circuit comprising: a magnetic core drive unit comprising a saturable magnetic core, a read-in control winding on said` core, a

sienes.F

read-out control Winding on said core, a first output winding on said core in which a halt current set pulse is induced when die core is set, a second output winding on said core in which a full current reset pulse is induced Wlien said core is reset, a read-in pulse circuit connected to said read-in control Winding for generating a set pulse which drives said core from a reset to a set state of saturation to generate a half current set pulse in said rlrst output winding, rectifier means in series with said tiret ouput winding for blocking current r'iow tberein only when tbe core is reset, a read-out pulse circuit connected to said read-out control winding for generating a reset pulse which resets core to generate a full current reset pulse in said second output winding, and rectifier means in series with said second output winding for blocking current flow in said second output winding only when core is set.

2. ln combination, a series of binary code bit storage units, eacli of said storage units having a pair o sig A t terminals tor respectively driving tbe storage unit 'om a rrst to a second binary state wben sct signals are sinultaneously fed thereto, one of the signal inputs of sai series or storage units eing connected to a common signal input terminal, means for generating set pulses coupled to e other signal input terminals of the series ot storage u its, a source or" pulses randomly related to said set pulses, `pulse forming responsive to each pulse output ci said source of pulses by generating a i persists at least until one set pulse is gen crated by said pulse generating means, iirst coincioe ce means liavn c inputs respectively coupled ial g a pair or to tbc outnut or tbe associated pulse orining means and said set 'p e generating means for providing a set pulse upon coincidence ot tbe input pulses thereto, and means coupling tbe output set pulses of said coincidence means to tbe common signal input terminal of said series oi storage units.

3. in combination, a series of binary code bit storage units, each ot said storage units having a pair of signal input terminals ror respectively driving tbe storage unit from a iirst to a second binary state when set signals are simultaneously led thereto, one of t'ne signal inputs 01"; sai series ot storage units being connected to a common signal input terminal, means Yfor generating set pulses col 4ded to tbe other signal input terminals of tbe series ot storage umts, a source of pulses randomly related to set pulses, pulse forming means responsive to eacli pulse generated by said pulse source tor providinn output '3 lse initiated by tbe beginning ot the latter coi cidence means baving a pair of inputs respectivelyv d to tbe output of tbe associated pulse ing means and said set ptlse generating means provi g a set pulse during coincidence of the input pulses thereto, means responsive to tbe trailing edge of the output set pulse of said coincidence means for terminating tbe output pulse of said associated pulse forming means, and means coupling tbe output set pulses of said coincidence to tbe common signal input terminal of said series of storage units.

4. A data storage system for storing binary coded information on the values of a number oi variables, said system com ing: variable responsive means for eacb variable providing a pulse output timed to indicate tbe value of the asso ted variable, a source of timing pulses, coding means co rising pulse counter means coupled to ng pulses for counting tbc same and providing at respective binary bit outputs tbereo a binary coded signa indicating tbe count accumulated therein, a storage rf 'ifi comprising a series of binary code bit storage uni-s for each variable, one such storage unit in 'b series being provided for each output oi said coding i of said storage units 1naving a pair ot signal input terrr nais for respecti 'ely driving tbe storage unit from a rst to a second binary state when set signals are *c sir ultane usly fed thereto, one ot tbe signal input terminals of cacb series ot storage units being connected to a common variable signal input yterminal and tbe corre sponding other signal ter i inals of tbe series of storage units being connected to respective common read-in signal input terminals, means for providing time gate pulses synchronously rer ed to said ti ting pulses, iirst coincidence means associated Witli each of said read-in signal input terminals ot tbe matrix and having a pair inputs respectively coupled to the associated output of said coding means and to said time gate pulse providing means for providing a iX set pulse upon coincidence of tbe input pulse from tbe latter means and a given binary output state of tiie associated output of said coding means, second coincidence means associated with each series of storage units and having a `pair of inputs respectively coupled to tbe output of tbe associated variable responsive means and said time gate pulse providing means for providing a matrix set pulse upon coincidence of tbe outputs of said variable responsive means and said time gate pulse providing means, and means coupling tbe output set pulses of said second coincidence means to tbe variable signal input terminal of tbe associated series of storage units.

5. A data storage system for storing binary coded information on tbe values or" a number ot variables, said system comprising: variable responsive means for eacb variable providing a oulse output timed to indicate the value of tbe associated vari ble, a source of timing pulses, coding means con pulse counter means coupled to said source of timing pulses tor counting tbe same and providing at respective binary bit outputs tbereoi a binary coded signal indicating tbe count accumulated tlierein, a storage matrix comprising a series of binary code bit storage units for each variable, one such storage unit in each series being provided for eacb output of said coding means, eacb ot said storage units having a pair of signal input terminals for respectively driving tbe storage unit from a nrst to a second binary state when set signals are simultaneously fed tnereto, one of tbe signal input terminais of each series of storage units being connected to a common variable signal input terminal and tbe other corresponding signal input terminals ot tbe various series ot storage units being connected to respective read-in signal input terminals, pulse multiplying means for providing time gate pulses at a multiple pulse repetition rate of that of said timing pulses, first coincidence means associated Witb eacli of said read-in signal input terminals or" tbe matrix and 1naving a pair of inputs respectively coupled to tbe associated output of said coding means and to said pulse multiplying means for providing a matrix set pulse upon coincidence of tbe input pulse from said pulse multinlying means and a given binary output state of tbe associated output of said coding means, second coincidence means associated with each series of storage units and having a pair of inputs respectively coupled to tne output of the associated variable responsive means and said common pulse multiplying means for providing a matrix set pulse initiating pulse at an output tbereot upon coincidence of the input pulses thereto, and a saturable core drive unit for eacli series of matrix storage units, said drive unit having a core made of a rectangular hysteresis material, an input Winding coupled to tbe output of tbe associated second coincidence means which drives the core from a reference to a set state of saturation and an output Winding coupled to tbe associa-ted common variable signal input terminal of the associated series of matrix storage uA Lts for feeding a set pulse tbereto when the core is set.

6. A data storage system for storing binary coded information on tbe values of a number of variables, said system comprising: variable responsive means `for eacn variable providing a pulse or out timed to indicate tbe Value of tbe associated variable, a source of timing pulses,

coding means comprising pulse counter means coupled to said source of timing pulses for counting tbe same and proaiazeea viding at respective binary bit outputs thereof' a binary coded signal indicatingthe count accumulated therein, a storage matrix comprising a series of binary code bit storage units for each variable, one such storage unit in each series being provided for each'output of said coding means, each of said storage units having a pair of signal input terminals for respectively driving the storage unit from a first to a second binary state when set signals are simultaneously fed thereto, one of the signal input terminals of each series of storage units being connected to a common variable signal input terminal and the other corresponding signal input terminals of the various series of storage units being connected to respective common readin signal input terminals, pulse delay means for providing time gate pulses at a multiple pulse repetition rate of that of said timing pulses and delayed with respect thereto, first coincidence means associated with each of said read-in signal input terminals of the matrix and having a pair of inputs respectively coupled to the associated output of said coding means and to said pulse delay means for providing a matrix set puise upon coincidence of the input pulse from said pulse delay means and a given binaryoutput state of the associated output of said coding means, second coincidence means associated with each series of storage units and having a pair of inputs respectively coupled to the output of` the associated variable responsive means and said common pulse delay means for providing a matrix set pulse upon coincidence of the input pulses thereto, and means coupling the output set pulses of said second coincidence means to the common variable signal input :terminal of the associated series of storage units.

7. In combination with a magnetic core matrix having columns and rows of magnetic core units each having a magnetic core made of a rectangular hysteresis material, first and second control winding means on the core for driving the core between opposite states of saturation when half current set pulses are simultaneously fed through the control winding means, and output winding means in which a signal is generated when the core is riven between opposite states of magnetic saturation, means connecting said first control Winding means in each column of core units to a common input, means connecting said second control winding means in each row of core units to a common input, and a read-in pulse circuit for feeding half current pulses to the common matrix inputs associated with either said coiumns or rows of core units, a control circuit associated with the common inputs of the other of same and comprising: a drive core unit associated with each of the latter core units, each of said drive core units comprising a magnetic core having a substantially rectangular hysteresis characteristic, a read-in control winding which drives the latter core from a first to a second state of saturation when a set pulse is fed thereto, and a first output winding into which is induced a half current matrix set pulse when the latter core is driven between said states of saturation, a pulse circuit Vcoupled to said first control winding for generating said drive unit set pulse, said pulse circuit comprising a time modulated pulse source, coincidence sensing means having a first and a second input, said first input being coupled to the output of said-time modulated pulse source, and a time gate pulse source for providing time gate pulses occurring concurrently with said half current puises of said read-in pulse circuit, the output or"y saidftime gate pulse source being connected to the second input of said coincidence sensing means, and said coincidence'sensing means having an output coupled to the read-in control winding of the associated drive core unit and providing a drive core set pulse when the time modulated and time gate pulses are concurrent. i

8. In combination with a magnetic core matrix having columns and rows of magnetic core units each having a magnetic core made of a rectangular hysteresis core material, first and second control winding means on the core 16 for driving the core between opposite states of saturation when half current set pulses are simultaneously fed through the control winding means, and output winding means in which a signal is generated when the core is driven between opposite states of magnetic saturation, means connecting said first control winding means in each column of core units to a common input, means connecting said second control winding means in each rowV or" core units to a common input, and a read-in pulse circuit for feeding half current pulses to the common matrix inputs associated with either said columns or rows of core units, a control circuit associated with the common inputs of the other of same and comprising: a drive core unit associatedv with each of the latter core units, each of said drive core units comprising a magnetic core having a substantially rectangular hysteresis characteristic, a read-in control winding which drives Ithe latter core from a first to a second state of saturation when a set pulse of at least a given minimum durationV is fed thereto, a first output winding into which is induced a half current matrix set pulse when the latter core is driven between said states of saturation, and a feedback winding, a pulse circuit coupled to said first control winding for generating said drive unit set pulse, said pulse circuit comprising a time modu-V lated pulse source, coincidence sensing means having a first and a second input, said first input being coupled to the output of said time modulated pulse source, a timeY gate pulse source for providing time gate pulses occurring concurrently with said half current pulses of said first read-in pulse circuit, the output of said time gate pulse source being connected to the second input of said coincidence sensing means, said coincidence sensing means having an output coupled to the read-in control winding of the associated drive core unit and providing a drive core set pulse when the time modulated and time gate pulses are concurrent for at least said minimum duration, and means coupling said drive core unit feedback winding to said coincidence sensing means for sustaining the output thereof while the drive core is being driven from said first to said second state of saturation. Y

9. In combination with a magnetic core matrix having columns and rows of magnetic core units'each having a magnetic core made of a rectangular hysteresis core material, first and secondcontrol winding means kon the core for driving the 'corebetween opposite states of-saturation when half current set pulses are simultaneously fed through the control winding means, and output winding means in which a signal is generated when the core is driven between opposite states of magnetic saturation, means connecting said first control winding means in each column of corev units to a common input, means connecting said second control winding means in each row of core units to a common input, and a first read-in pulse circuit for feeding half current pulses to the common matrix inputsl associated with either said columns or rows of core units, a control circuit associated with the common inputs of the other of same and comprising: a drive core unit associated with each of the latter core units, each of said drive-core units comprising a magnetic core having a substantially rectangular hysteresis characteristic, a read-in control winding which drives the latter core from a first to a second state of saturation when a set pulse is fed thereto, a reset control winding which resets the core when a reset pulse is fed thereto, a first output winding into which is induced a half current matrix set pulse when the latter core is driven between said states of saturation,` a rectifier connected between said first output' winding and the associated matrix input for blocking induced current when the latter core is reset to said first state of saturation, a second output windinginto which is inducedv a full current matrix reset pulse'capable of resetting all the associated matrix cores, a rectifier connected between said second output winding and Ythe associated matrix inputV for blocking induced current when the drive unit core is set, a variable responsive pulse ciri7 cuit coupled vto said rst control winding for generating said drive unit set pulse, said variable responsive pulse circuit comprising a time modulated pulse source which provides a pulse timed in accordance with the value of the associated variable, coincidence sensing means having a first and a second input, said rst input being coupled to the output of said time modulated pulse source, a time gate pulse source for providing time gate pulses occurring concurrently with said halr" current pulses of said tirst read-in pulse circuit, the output of said time gate pulse source being connected to the second input of said coincidence sensing means, said coincidence sensing means having an output coupled to the read-in control Winding of the associated drive core unit and providing a drive core 1.3 set pulse When the time modulated and time gate pulses are concurrent, and a read-out pulse circuit coupled to said drive unit reset control Winding for providing at a selected time a reset pulse which resets said drive unit core and the associated matrix core units.

References Cited in the rile of tnis patent UNTED STATES PATENTS 2,772,370 Bruce Nov. 27, 1956 2,901,735 Lawrence Aug. 25, 1959 2,922,145 Bobeck Ian. 19, 1960 2,939,114 Bobeck et al May 31, 1960 2,956,271 Kelier Oct. l1, 1960 

1. A CONTROL CIRCUIT FOR SETTING AND RESETTING MATRIX MAGNETIC CORE STORAGE UNITS, SAID CONTROL CIRCUIT COMPRISING: A MAGNETIC CORE DRIVE UNIT COMPRISING A SATURABLE MAGNETIC CORE, A READ-IN CONTROL WINDING ON SAID CORE, A READ-OUT CONTROL WINDING ON SAID CORE, A FIRST OUTPUT WINDING ON SAID CORE IN WHICH A HALF CURRENT SET PULSE IS INDUCED WHEN THE CORE IS SET, A SECOND OUTPUT WINDING ON SAID CORE IN WHICH A FULL CURRENT RESET PULSE IS INDUCED WHEN SAID CORE IS RESET, A READ-IN PULSE CIRCUIT CONNECTED TO SAID READ-IN CONTROL WINDING FOR GENERATING A SET PULSE WHICH DRIVES SAID CORE FROM A RESET TO A SET STATE OF SATURATION TO GENERATE A HALF CURRENT SET PULSE IN SAID FIRST OUTPUT WINDING, RECTIFIER MEANS IN SERIES WITH SAID FIRST OUTPUT WINDING FOR BLOCKING CURRENT FLOW THEREIN ONLY WHEN THE CORE IS RESET, A READ-OUT PULSE CIRCUIT CONNECTED TO SAID READ-OUT CONTROL WINDING FOR GENERATING A RESET PULSE WHICH RESETS SAID CORE TO GENERATE A FULL CURRENT RESET PULSE IN SAID SECOND OUTPUT WINDING, AND RECTIFIER MEANS IN SERIES WITH SAID SECOND OUTPUT WINDING FOR BLOCKING CURRENT FLOW IN SAID SECOND OUTPUT WINDING ONLY WHEN SAID CORE IS SET. 